LDO Regulator circuit

Recently the author had to adapt  a standard schema configuration  (which often uses an npn bipolar) so as to operate as a low-dropout (LDO) regulator. The schema shown here uses that rarity,  a depletion-mode MOSFET to implement the LDO function. What to do when you have to derive an analogue supply voltage  (close to +5 V) from an existing ‘digital’ 5-volt rail, ensuring sufficient decoupling between the two? One answer is  to step up and then use a linear regulator to step back down. However, if around 4.5 volts will suffice then an alternative is a home-made LDO regulator. The schema is usually a fairly  standard shape typically a npn transistor (with base-current limiting resistor) is used.

Circuit diagram :

 

LDO Regulator Circuit Diagram

Initially, it would appear that this design suffices after all, the text books say the saturation voltage  is around 0.2 V. Unfortunately,  this is no longer true when the collector is tied directly to the positive supply. An enhancement-mode  MOSFET suffers  similar disadvantages: with the drain tied High you need greater than  drain  potential at the gate to achieve low RDS(on). Enter that seldom-used beast the depletion-mode MOSFET! Depletion-mode MOSFETS are ‘on’ even  when  V gs = 0,  and  you have to back-bias the gate  to achieve an increase in channel resistance.In the schema shown the BSS139,  an NMOS depletion device, operates with the gate forward biased. With a load of 10 mA, the measured FET resistance was  38 ohms.