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Simple Frequency Comparator II Wiring diagram Schematic
Should the count be more than 1031 than the latch IC4c/IC4a is set to indicate count too high (F (measure) F (ref)) and if the count is less than 1017 then IC3/IC4b indicate count too low (F (measure) F (ref). These signals are latched by IC5 at the end of each period by the latch signal from IC6e. When the two frequencies are within + or - 0.6% the LSBs of the counter IC2 are decoded and latched by IC7 and displayed on LEDs IC6c resets the counter after latching the data.
Simple Frequency Comparator II Wiring diagram Schematic
This is a Simple Frequency Comparator II Circuit Diagram. The schema provides unambiguous LED + or - bar readout with steps of 0.1%. The reference frequency is multiplied by the PLLIC1 and divider IC9 to output 64 ? F (ref) and this is then gated by dividing F (measure) by 32 in IC8 thus is F (ref) = (measure) then IC2 counts 1024 pulses.
Simple Frequency Comparator II Circuit Diagram
Should the count be more than 1031 than the latch IC4c/IC4a is set to indicate count too high (F (measure) F (ref)) and if the count is less than 1017 then IC3/IC4b indicate count too low (F (measure) F (ref). These signals are latched by IC5 at the end of each period by the latch signal from IC6e. When the two frequencies are within + or - 0.6% the LSBs of the counter IC2 are decoded and latched by IC7 and displayed on LEDs IC6c resets the counter after latching the data.
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